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SI9117
Vishay Siliconix
High-Frequency Converter for Telecom Applications
FEATURES
D D D D On-board high-voltage, 1-W Switching FET Switching Frequencies of Up to 1 MHz Synchronization Capability Easily Compensated Current-Mode Operation D D D D Operates with Input Voltages Up to 200 V 1.8-MHz Error Amplifier Soft-Start Latched SHUTDOWN
DESCRIPTION
The SI9117 high-efficiency converter for telecom systems running off 48 V is ideal for emerging applications such as interactive video (IV) set-top boxes and microcell base stations, such as those used for Personal Communications Systems (PCS). IV set-top boxes and microcell base stations typically require less than 15 W of power and have access to the analog telephone line power. Both IV set-top boxes and microcell base stations process extremely low-level, modulated analog signals (on the order of mVs), making the frequency and energy content of radiated and conducted noise a major issue. These application circuits are also constrained in terms of available board space and place a premium on minimal footprint. Processing high-frequency, modulated analog signals for video or RF requires receivers with sensitivities in the range of 0.5 to 25 mV. At these levels, noise generated by switchmode power conversion can impair the signal recovery process. Controlling radiated noise is a matter of proper layout and shielding. Controlling conducted noise is a matter of limiting its energy and isolating the conducted energy's fundamental and harmonic frequencies to bands which will not affect the frequencies of interest. The high-frequency, synchronized switching of the SI9117 enables this design requirement. First, for a given output current, high-frequency switching attenuates output ripple, minimizing conducted energy. Second, synchronizing the high switching frequency to an external frequency allows the fundamental and its harmonics to be moved out of range of the frequency bands of interest. An additional benefit of high-frequency switching is reduced size and cost of the inductor and the output filter capacitance. In addition to these mandatory design considerations, the SI9117 is easy to design with and compensate, and takes a minimum of board area to implement: an important benefit in high-volume/small-package applications such as set-top boxes and microcell base stations. The SI9117 is available in both standard and lead (Pb)-free packages.
The combination of an on-board, high-voltage, 1-W switch and a PWM IC with operational input voltage of 200 V allows operation off of the analog telephone line, even with the worst case battery voltage and ringing voltage. Once the converter has started up, a simple bootstrap circuit can provide power to the IC by raising the source voltage of the n-channel, depletion mode, start-up FET above its gate voltage of 9.2 V. This technique lowers system costs, reduces the area required for circuit implementation, and minimizes circuit power consumption.
APPLICATIONS CIRCUIT
VIN + VOUT
1 2 3 SYNC 4 5 6 7 8
16 15 14 13 12 11 10 9 NC SHUTDOWN
SI9117
Document Number: 70027 S-40750--Rev. E, 19-Apr-04
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SI9117
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to -VIN VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V +VIN (Note: VCC < +VIN + 0.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V Logic Input (SHUTDOWN, SYNC) . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Linear Inputs (FEEDBACK, SENSE, SOFT-START) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . . . . . . . . 5 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150_C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85_C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C Drain-Source Voltage (TA = 25_) (VDS)a . . . . . . . . . . . . . . . . . . . . . . . . . 200 V Continuous Drain Current (TA = 25_) (ID)a . . . . . . . . . . . . . . . . . . . . . . . 1.0 A Power Dissipation (Package)a 16-Pin SOIC (Y Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Thermal Impedance (QJA) 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140_C/W Notes a. Device mounted with all leads soldered or welded to PC board, t v 2 sec. b. Derate 7.2 mW/_C above 25_C.
RECOMMENDED OPERATING RANGE
Voltages Referenced to -VIN VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 V to 16.5 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V to 200 V fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 kHz to 2 MHz ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 kW to 1 MW COSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 pF to 200 pF Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC - 4 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC
SPECIFICATIONS
Test Conditions Unless Specified Parameter Reference
OSC Disabled, TA = 25_C Output Voltage Short Circuit Current Load Regulation VR ISREF DVR/DIR OSC Disabled Over Voltage and Temperature Rangesc VREF = -VIN IREF = 0 to -1 mA 3.94 3.88 4.0 4.0 -30 10 4.06 4.12 -5 40 V mA mV
Limits Mina Typb Maxa Unit
Symbol
Oscillator Disabled -VIN = 0 V, VCC = 10 V
Oscillator
Initial Accuracy Voltage Stabilityc Temperature Coefficientc fOSCd Df/f OSC TC ISYNC(M) ISYNC(S) ROSC = 374 kW , COSC = 200 pF ROSC = 70 kW , COSC = 200 pF ROSC = 70 kW , COSC = 200 pF Df/f = [f(16.5 V) - f(9.5 V)] / f(9.5 V) -40 v TA v 85_C, fOSC = 100 kHz VROSC v 5 V VROSC = VCC "1.0 90 450 100 500 1 200 "3.0 "1 "500 110 550 2 500 kHz % ppm/_C mA nA
Sync Output Current (Master Mode) Sync Output Current (Slave Mode)
Error Amplifier (COSC = -VIN OSC Disabled)
Input BIAS Current Input OFFSET Voltage Open Loop Voltage Gainc Unity Gain Bandwidthc IFB VOS2 AVOL BW IOUT PSRR Source (VFB = 3.5 V, NI = VREF) Sink (VFB = 4.5 V, NI = VREF) 9.5 V v VCC v 16.5 V 1.0 50 65 1.8 VFB = 5 V, NI = VREF <1.0 "5 80 2.7 -2.7 2.4 80 -1.0 "200 "25 nA mV dB MHz mA dB
Output Current Power Supply Rejection
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Document Number: 70027 S-40750--Rev. E, 19-Apr-04
SI9117
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified Parameter Pre-Regulator/Start-Up
Input Leakage Current Pre-Regulator Start-Up Current VCC Pre-Regulator Voltage VPR -VUVLO (Turn-On) Undervoltage Lockout Hysteresis +IIN ISTART VPR VDELTA VHYST +VIN = 200 V, VCC w 10 V +VIN = 48 V, tPW v 300 ms, VCC = VUVLO +VIN = 48 V 8 8.8 0.1 0.18 t1 20 9.1 0.25 0.28 9.4 0.7 0.4 V 10 mA mA
Limits Mina Typb Maxa Unit
Symbol
Oscillator Disabled -VIN = 0 V, VCC = 10 V
Supply
Supply Current ICC CLOAD v 50 pF fOSC = 100 kHz fOSC = 500 kHz 1.8 3.7 2.5 4.5 mA
Protection
Current Limit Threshold Voltage Current Limit Delay to Outputc SHUTDOWN Logic Threshold SHUTDOWN Delay to Latched SHUTDOWN Pull-Up Current Soft-Start Current Output Inhibit Voltage Outputc VSENSE td VSD tSD ISD ISS VSS(off) Soft-Start Voltage to Disable Driver Output See Figure 2 VSD = 0 V 12 12 VFB = 0 V, NI = VREF VSENSE = 1.5 V, See Figure 1 1.035 1.16 105 2.8 0.21 22 22 1.6 1.30 130 0.5 1.0 30 30 0.5 V ns V ms mA V
Switch
Zero-Gate Voltage Drain Current Drain-Source On-State Resistancee IDSS rDS(on) VDS = 200 V, VGS = 0 V, TA = 25_C VGS = 10 V, ID = 1.0 A, TA = 25_C 0.7 0.8 5 1 mA W
Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. Guaranteed by design, not subject to production test. d. CSTRAY v 5 pF on COSC. e. Pulse Test; Pulse Width v 300 ms, Duty Cycle v 2%.
TIMING WAVEFORMS
1.5 V- CURRENT SENSE 50% 0 td
VCC tr = 10 ns SHUTDOWN 50% tSD VCC
tf = 10 ns
DRAIN 0 10%
DRAIN 0 10%
VCC
Document Number: 70027 S-40750--Rev. E, 19-Apr-04
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SI9117
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TYPICAL CHARACTERISTICS
Output Frequency
1000 COSC = 47 pF 100 pF f OUT - Output Frequency (kHz) 150 pF I CC - Supply Current (mA) 200 pF 12 16
Supply Current vs. Output Frequency
VCC = 12 V
100
8
4
10 10 100 ROSC - Oscillator Resistance (k) 1000
0 0 200 400 600 800 1000 fOUT - Output Frequency (kHz)
7
Supply Current vs. Supply Voltage
1.25
Output Frequency vs. Supply Voltage
ROSC = 60 kW COSC = 47 pF
fOUT = 250 kHz I CC - Supply Current (mA) 6 f OUT - Output Frequency (MHz) 9 10 11 12 13 14 15 16 17 1.00
0.75
5
0.50
4
0.25
3 VCC - Supply Voltage (V)
0.00 8 10 12 VCC - Supply Voltage (V) 14 16
1.2 r DS(on) Drain-Source On-Resistance ( W ) -
Drain-Source On Resistance vs. Temperature
26
ISS (Soft-Start) vs. Temperature
1.0
I SS - Soft Start Current ( m A) -25 0 25 50 75 100
24
22
0.8
20
0.6
18
0.4 -50
16 -50
-25
0
25
50
75
100
TJ - Temperature (_C) www.vishay.com
TJ - Temperature (_C) Document Number: 70027 S-40750--Rev. E, 19-Apr-04
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SI9117
Vishay Siliconix
TYPICAL CHARACTERISTICS
Error Amp Gain and Phase
-20 -40 -60 Phase ( _ ) -80 Phase -100 -120
100 80 60 Gain (dB) 40 20 0 -20 0.1
4020 4010 4000 3990 3980 3970 3960 -50
Reference Voltage vs. Temperature
Gain
1
10
100
1000
-140 4000
V REF - Reference Voltage (mV)
-25
0
25
50
75
100
f - Frequency (kHz)
215 f OSC- Oscillator Frequency (200 kHz)
Oscillator Frequency vs. Temperature
1050 f OSC- Oscillator Frequency (1 MHz)
210
f = 1 MHz
1025
205
1000
f = 200 kHz 200 975
195 -50
-25
0
25
50
75
950 100
TJ - Temperature (_C)
Document Number: 70027 S-40750--Rev. E, 19-Apr-04
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SI9117
Vishay Siliconix
PIN CONFIGURATION AND ORDERING INFORMATION
16-Pin SOIC
SS ROSC COSC SYNC V- VCC ISENSE S 1 2 3 4 5 6 7 8 Top View 16 15 14 13 12 11 10 9 COMP FB NI VREF SD V+ NC D
ORDERING INFORMATION
Part Number
SI9117DY SI9117DY-T1 SI9117DY-T1--E3 -40 to 85_C SOIC-16
Temperature Range
Package
PIN DESCRIPTION
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Symbol
SS ROSC COSC SYNC V- Vcc ISENSE S D NC V+ SD VREF NI FB Comp
Description
Generates a 20-mA current source. IC turns or when capacitor is charged to 4.6 V. Sets the oscillator charging current. Use the "oscillator frequency vs. ROSC" curve in The Typical Characteristics section. Sets oscillator frequency. Use the "Oscillator frequency vs. ROSC" curve in the Typical Characteristics section along with equations 1 and 2 in the Oscillator section of the Description of Operations. Synchronization input overrides the oscillator. Slave mode operations is possible, as is operation of the converter at duty cycles >50%. See Oscillator section of the Description of Operations. Ground or negative mode of input power supply. Bootstrap power supply pin Current-mode sense input Switch FET source. Switch FET drain. No connect: for test purposes only. (Normally left open) High voltage (up to 200 V) power supply input. Shutdown. Logic low shuts down the controller. Output of the 4-V reference sources 5 mA. Non-inverting input of the error amplifier. A resistor divider from the reference can be used to set this voltage. Inverting input to the error amplifier; used to maintain output regulation. Output of the error amplifier. Used to provide compensation for the converter's feedback control loop.
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Document Number: 70027 S-40750--Rev. E, 19-Apr-04
SI9117
Vishay Siliconix
BLOCK DIAGRAM
V-
VCC Ref
VREF
20 mA V+ SS Q V- S 9.2 V SD - + 2V 1.25 V NI COMP
- + - + 20 mA 0.2 V
R
FB ROSC Oscillator COSC B2 - + S Q R - + NC D S
ISENSE
SYNC
APPLICATIONS
Description of Operation The SI9117 is a current mode PWM IC combined with an integrated 1-W 200-V MOSFET. Current mode operation offers the following advantages: D Cycle-by-cycle current limit protection D Simple loop compensation, eliminating the effect of output inductor D Excellent fast transient response due to inner control loop D Automatic input voltage feed-forward compensation In addition, the SI9117 is duty-cycle limited to avoid core saturation.
Document Number: 70027 S-40750--Rev. E, 19-Apr-04
High Voltage Pre-Regulator All switchmode power supplies face a start-up problem caused by the large difference between dc bus voltage and the VCC power rail for supplying the control circuit. The traditional technique has been to keep the control circuit in "sleep mode," while a small amount of energy is used to "top up" a large enough electrolytic capacitor to get the circuit started. When the circuit starts operating, a winding on the transformer is then used to power the control circuit. Disadvantages with this type of circuit include delayed start-up and large required capacitances for guaranteed operation over the full voltage range. The SI9117 overcomes these problems by using low power consumption, BiC/DMOS circuitry, and a unique high-voltage depletion mode MOSFET (see Figure 1).
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SI9117
Vishay Siliconix
To Internal Circuits VCC +VIN Transformer Winding
300 mV - CIN + 0.2 V - + UVLO
9.2 V -VIN
CVCC
FIGURE 1. Start Circuit
When power is first applied, the depletion transistor is on, and current flows from the input capacitor CIN into the VCC capacitor CVCC until VCC reaches 9.2 V. The converter transformer will then supply the VCC through a bias winding, which will raise VCC to a level higher than 9.2 V. Ideally this will be between 11 and 13 V, thus turning off the high-voltage depletion mode MOSFET. The 9.2-V threshold has a hysteresis of 300 mV to prevent oscillations when the transition voltage is not clearly defined or when high-line supply impedance is encountered. For applications where the input dc voltage is not high, and the chip power consumption is not excessive, the feedback winding can be eliminated. In such cases, the pre-regulator circuit will behave just like a linear regulator with 9.2-V output and 10-kW series resistance. In this case, the parameters to be considered are the dropout voltage at lowest line condition and the power dissipation at highest voltage. The high-voltage depletion mode MOSFET contains an internal body diode, and in situations where the VCC is being powered from a laboratory supply, care must be taken to avoid loading the +VIN rail beyond the current rating of this device. Typically, the reverse characteristics of the device will generate a voltage of 3.4 V on Pin 11 with 10-kW load when powering VCC from a lab supply. In some applications it is necessary to inhibit the start of a converter until a high enough voltage is present on the supply bus. This is the case for the following reasons: D Circuitry fed from a high line impedance such as a telephone line will have difficulty starting, since the converter will behave like a negative impedance. As the dc voltage decreases, the input current increases because constant power is drawn. This causes severe oscillations,
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and can in some instances have a destructive effect on the converter. D During start-up, the SI9117 will begin operation as soon as the UVLO threshold is reached. Since the converter is designed to operate over a much higher range--for example, from 36 to 72 V--then between 10 and 36 V input the output voltage will be out of regulation and undefined. In some cases, digital circuitry will not accept this mode of operation, and system faults will be encountered without a RESET watchdog circuit. To overcome these problems, a Zener diode of suitable value VZ can be placed in series with the +Vin pin, preventing start-up until VZ + 9.2 V is reached. Shutdown The shutdown pin is configured to allow fast latched termination of the output pulse. The delay from shutdown to output is typically 300 ns. This delay is short enough to allow this pin to be used for over-voltage applications where fast orderly shutdown is desirable: for example, when control of the feedback loop is lost. Using an opto-coupler and a TL431, interface is easy (see Figure 2). Once latched, the shutdown can only be reset from the UVLO circuit by re-cycling the power. In the event of an over-voltage, the latch can be reset by momentarily pulling the VCC to a value lower than the UVLO threshold. This approach will generally be acceptable, since the feedback winding will not be supplying power, and the only power maintaining the latch will be supplied by the depletion start transistor. Note, however, that this action will still be subject to the power dissipation limits of the SI9117 package and should ideally be applied as a short fast pulse.
Document Number: 70027 S-40750--Rev. E, 19-Apr-04
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SI9117
Vishay Siliconix
VCC +OP VOUT
20 mA -OP
S Q R 6 5 4 UV-Low NC 2 3 1
SI9117
TL431
FIGURE 2. Shutdown
Reference The reference voltage is a fully buffered band gap type which can source 5 mA over the specified voltage tolerance range. The reference should be well de-coupled to prevent instability and jitter. A ceramic 100-nF or small tantalum is recommended, depending on the de-coupling present on the supply pins. Error Amplifier The error amplifier consists of a PMOS input folded cascade gain stage followed by a class AB unity gain amplifier. Typical open loop voltage gain is 77 dB, and unity gain bandwidth is typically 2.7 MHz. The soft-start circuit (see Pin 1 description) forces the output to within 0.7 V above ground, and additional clamp diodes limit the positive output excursion to within 2xVBE above VREF . Operation at high frequency allows high closed loop bandwidths and permits excellent transient response to both input and output changes. Under normal operation, a small 100-pF bypass capacitor is recommended from NINV to Comp to increase high-frequency noise rejection. This should be calculated, however, in conjunction with the loop dynamics. Soft-Start The soft-start circuit is designed to help dc-to-dc converters start in an orderly manner and reduce component stress. The output of the error amplifier is clamped by a PNP transistor. The external capacitor CSS is supplied by a 20-mA current source and will charge linearly to 4.6 V. In the event of an under-voltage lockout (or during start-up), this capacitor is held low. Soft-start is a very important feature and has many beneficial effects, especially in applications connecting to telecom lines where source impedances are high. In such
Document Number: 70027 S-40750--Rev. E, 19-Apr-04
cases, there is an initial start-up current caused by the input capacitor, followed by a secondary peak caused by the converter running at maximum duty cycle while trying to reach regulation. Where large output capacitances and peak loads are encountered, oscillations may occur. These can be prevented with the use of long soft-start times. The soft-start pin can also be used as a non-latching shutdown pin by connecting it to -VIN. This approach allows a shutdown with soft re-start.
FBK
NINV
1.5 kW
+ -
Comp
SoftStart
FIGURE 3. Operational Amplifier
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SI9117
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Feedback
Error Amp
The current programmed by RT defines the charging current of CT and the on and off times with the following design equations:
4.6 V
VREF
Comparator
TON +
1.025 x RT x CT 8 where Rql = 25 W
(1)
20 mA
TOFF + 5 x Rql x CT 1 1 FOSC + 2 x T ) TOFF ON
(2)
(3)
CSS
UV-low
Actual values taken from a prototype board have been plotted (Figure 6), and are a close match (except for 47 pF, where stray parasitics have a more significant effect).
FIGURE 4. Soft-Start
In certain circumstances, such as current limiting, it may be desirable to change the frequency of the converter for a period of time to overcome current tails (see Figure 14 for further explanation). With the SI9117, this is easily done by adding or subtracting some current into the RT terminal: D The charging current in CT is set by 8 RT.
Oscillator The oscillator circuit uses external timing components RT and CT. An internal divide-by-two prevents pulses with greater than 50% duty cycle, so that core saturation can be avoided. When the RT terminal is connected to VCC, comparator C2 disconnects the oscillator output from the SYNC terminal using SW1, and allows an external oscillator circuit to take control of the current mode comparator circuit.
D The voltage at the RT terminal is 4 V, as supplied by an internal emitter follower from the reference. The frequency can be changed easily by supplying some of the current into RT from the VCC rail, thus "starving" the internal current source, and slowing the frequency down. (See Figure 7.)
I1 C1 VREF Q2 C2 B1 B2 D U1 Q SW1 B3 SYNC
CLK RT CT Q1 Q I2
FIGURE 5. Oscillator
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SI9117
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1000 COSC = 47 pF 100 pF f OUT - Output Frequency (kHz) 150 pF 200 pF R1 120 k CVCC 1 mF SW1 RT 68 k
VCC
100
Rt Ct CT -VIN
D1
10 10 100 ROSC - Oscillator Resistance (kHz) 1000
SW1 Closed = Frequency High SW1 Open = Frequency Low
FIGURE 6. Oscillator Frequency Selection
FIGURE 7. Frequency Shifting Using Rt Current Change
Ct
Rt 1 2 3 4 5 6 7 8 SS
SI9117
COMP FB NI 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 SS
SI9117
COMP FB NI 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 SS
SI9117
COMP FB NI 16 15 14 13 12 11 10 9
ROSC COSC
ROSC COSC
ROSC COSC
SYNC VREF V- VCC ISENSE S IC1 SD V+ NC D
SYNC VREF V- VCC ISENSE S IC2 SD V+ NC D
SYNC VREF V- VCC ISENSE S IC3 SD V+ NC D
FIGURE 8. Oscillator Synchronization
The current in RT is set by V = IR where V = 4 V and R = RT. Using a diode, and some type of switch, the frequency can be easily changed: when SW1 is closed, D1 is reverse biased, and has no effect on RT. When SW1 is open, current flows through R1 and D1 into RT and removes some of the current supplied by the internal emitter follower.
Synchronization The SYNC input allows operation from a master clock as the connection is made after the divide-by-two. As a result,
Document Number: 70027 S-40750--Rev. E, 19-Apr-04
synchronization in both frequency and phase is possible. This unique feature is important to systems designers who use multiple converters, where noise caused by an unsynchronized "beating" effect is present and causes difficult EMI/EMC problems. If an external clock is used, duty cycles of > 50% are possible due to the position of the SYNC pin , after the divide-by-two. Where > 50% conduction is used, core reset must be allowed, in order to prevent core saturation. Synchronization is in master/slave mode, with one device (the "master") setting the switching frequency and others (the "slaves") with disabled oscillators locked to it. Alternatively, all devices can be clocked using a master oscillator. (See Figure 8.)
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SI9117
Vishay Siliconix
During slave mode, the unused CT pin should be connected to ground, and the RT to VCC. VIN and VDD These pins are used for powering the SI9117 and should consequently be well de-coupled. In selecting the right de-coupling, the MOSFET gate drive requirements should be considered, as the de-coupling capacitor will also have to supply the required peak current. Generally speaking, the best combination would be a 1- to 10-mF electrolytic for bulk energy and a 100-nF ceramic for high-frequency bypass. The VCC rail should be carefully observed at the switch on and off occurrences using ac de-coupling, and the peak voltage spikes should be measured. These should be less than 200 mV. Excessive noise on the VCC will appear on other pins and may cause instability or jitter on the control waveforms. Switch The switch FET is designed specifically for converters in the 5to 10-W power range. It has a 200-V VDS rating with 1-W rDS(on). Using the Gate charge curve, for a gate drive of 12 V from the SI9117, the total gate charge for 100-V VDS will be 10 nC. From Q = i x t, it is easy to deduce that with a 400 mA internal gate drive, a time of 50 ns will be obtained (see Figure 9). Sensed current waveforms often have leading-edge spikes or noise caused by reverse recovery of rectifiers, equivalent capacitive loading on the secondary, and inductive circuit effects. Inductive sense resistors must not be used, as they cause large damaging spikes and distort the sensed waveforms. These spikes can confuse the PWM comparator into believing that an overload condition is present. In addition, the SI9117 uses a single pin (-Vin) for all the return current requirements, including the output driver. As a result, the current pulse from the gate charge transfer into the MOSFET will appear on the sense pin and be filtered out. Waveform A (Figure 11) has an ideal textbook appearance, but is in fact rarely encountered. Waveforms B and C are typical yet close to the threshold limit, and thus could lead to instability. The addition of a simple RC network on the sensed waveform suppresses this leading-edge spike. The low pass filter should be selected so that only the leading-edge spike is suppressed and the overall waveform is not distorted. The waveform must contain a clean rising slope for the error amplifier to intersect. If the RC time constant is too long, then the waveform will be distorted and lead to falling-edge jitter on the turn-off edge. Slope compensation can also be used to eliminate noise or jitter. A sample of the oscillator voltage is superimposed on the error amplifier to produce a clean crossing of the thresholds and to avoid any hunting. The SI9117 has built-in leading-edge blanking/ suppression to eliminate some of the effects of these spikes. The two comparators used to operate the circuit have different delay times as follows: D The current mode comparator needs more noise immunity, and therefore has a deliberately slower delay time to block out noise and spikes which are present on the leading edge. Typical delay times should be around 100 ns.
0 4 8 12 16
current can supply all the necessary information if sampled in the MOSFET as a scaled equivalent. Certain precautions are necessary, however, due to data distortion, noise, and the rarity of ideal operating conditions.
20 VDS = 100 V Gate-to-Source Voltage (V) 16
12
8
4
0
Qg - Total Gate Charge (nC)
FIGURE 9. SI9117 Internal MOSFET Gate Charge
D The peak current limiting comparator has the fastest response time, since it is used only to protect the circuit in the event of an overload. The delay times for this comparator should be around 70 ns. High-Frequency Design Requirements
Current Sense The current sense comparator performs the current mode control function by comparing the output of the error amplifier (VC) with the current in the output inductor. It is impractical to measure the output inductor current, but the rising slope of the
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When designing converters for high switching frequency, a certain discipline is required to determine the right choice of components. This process should be an iterative choice and the board layout should be properly planned before CAD layout is undertaken.
Document Number: 70027 S-40750--Rev. E, 19-Apr-04
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SI9117
Vishay Siliconix
L iL OSC
VOUT
1 VC 2
3
iL iDC ID
VC RSENSE ID
FIGURE 10. Constant Frequency Current Mode Control
A
B
C
FIGURE 11. Current Waveforms
FIGURE 12. Current Sense Filtering Network
Layout Considerations The main current loop flows from the input capacitor--through the transformer, MOSFET, and sense resistor--and returns to the capacitor. This current will have high rates of change and associated fast voltage and current edges. It is essential to avoid the injection of noise into the other circuitry. To prevent this result, a "fishbone" type arrangement is
recommended (Figure 13). Designers are encouraged to separate different grounds with "imaginary" dummy resistors. These can be removed at a later stage. Main current loops must be designed to be as short as possible: from CIN to the transformer, through the MOSFET and Sense resistor, and back into CIN. It is obvious that signals switching 50 V or 1 A in 25 ns should not be mixed with signals that are controlling a closed-loop, high-gain feedback system which is capable of regulating the output voltage to less than 1 mV.
Document Number: 70027 S-40750--Rev. E, 19-Apr-04
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SI9117
Vishay Siliconix
+
Cref
SI9117DY
Css Cin 1 2 3 4 5 Cfilt 6 7 8 Rfilt SS ROSC COSC SYNC V- VCC ISENSE S COMP FB NI VREF SD V+ NC D 16 15 14 13 12 11 10 9 Tx1
Volts
Current Tail
Amps 100% 105% 115% Document Number: 70027 S-40750--Rev. E, 19-Apr-04
- Rsense
FIGURE 13.
FIGURE 14.
Choosing the Switching Frequency When selecting the switching frequency, it is usually best to choose the lowest possible frequency that the design solution will accept. In PWM control topologies, the maximum switching frequency will be strongly governed by short circuit behavior. When a short circuit is applied to the output, the control circuit is required to reduce the duty cycle to the smallest possible value to maintain constant current operation (Figure 14). Ideally, the converter should deliver 105% of the output current within regulation and no more than 115% under short circuit. At 500 kHz, the period of conversion is 2 ms and the maximum on time is 1 ms. High minimum duty ratios will result in current tails and require rectifier oversizing to avoid destructive currents under overload conditions. The SI9117 has a sync-to-output delay of less than 70 ns, so the minimum duty cycle for operation at 500 kHz would be 70 ns/1 ms = 7%. This minimum should be considered when the short circuit current is determined. Designers should note that a shunt placed across the output of the converter is probably not a realistic load in the event of a failure, and the real circuit impedance will probably be substantially lower. In such circumstances, it may be necessary to shift the frequency of the converter to a lower value during overload. Frequency shifting can be accomplished by altering the steady state values of the oscillator programming components (see oscillator section, Figure 7).
Short Circuit Behavior Short circuit behavior is different for both common topologies, and must be paid special attention. D In flyback converters, all windings appear in "parallel" with each other. When one winding is shorted, all other flyback windings are also shorted through it. In multiple output converters, therefore, any single winding without a separate secondary current-limiting protection will "drag down" all the other windings. As a result, if a bias winding is used to power the control circuit, it will stop delivering power. When this occurs, the SI9117 depletion device will turn on and regulate the supply rail to 9.2 V, as in its normal starting mode. In this event, designers should calculate the worst-case power dissipation caused by the voltage drop across the depletion transistor at the highest applied voltage across it and with the current flowing through it. D In forward converters, traditionally the bias winding is also taken in forward conduction mode, but without any series inductance. In the event of a short circuit, the pulse width is reduced to minimum, but it is sufficient to supply enough power to the control circuit. This is an advantage, and avoids the problems encountered with flyback converters. Power may also be taken in flyback mode, however, when the duty cycle is low. There will be very little flyback voltage present, since the applied volt/microseconds is low and the core need not, therefore, fly back very far to reset.
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14
SI9117
Vishay Siliconix
J1 CON4 1 2 3 4
D5 D5SC4M
10 mH 1 2 3 4
J2 CON4
C1 3.3 mF C14 6.8 mF 16 V R2, 1.5 W C3 82 pF R3 470 W D1 LS4148
R17 180 W R16 22 kW R14 1 kW
R5 180 W
SI9117
9 10 11 12 13 14 R13 2.2 kW C10 100 pF 15 16 D NC V+ SD VREF NI FB COMP C7 82 pF S ISENSE VCC V- SYNC COSC ROSC SS 8 7 6 5 4 3 2 1
C17 2.2 mF
TCMT1020 C4 100 nF C12 100 pF IC3 R18 1 kW C8 56 pF
C11 10 nF
IC4 TL431CLP R15 22 kW
R7, 120 kW
C6 100 nF
C5 10 nF
R6 56 kW
R8 6.8 kW
"Y" Grade Capacitor Typically 4.7 nF
FIGURE 15. Complete Schematic Diagram
Document Number: 70027 S-40750--Rev. E, 19-Apr-04
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15

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